Huawei unveils Tau Scaling Law chip framework to reach 1.4nm density by 2031

Huawei has officially revealed a massive shift in how the company designs and builds microchips. Speaking at a major worldwide electronics symposium in Shanghai, a top executive from the company introduced a brand-new semiconductor framework called the Tau Scaling Law. This new design rule aims to push the hardware limits of the company to match highly advanced global standards over the next few years.

Moving from physical size to time efficiency

For decades, the global semiconductor industry relied strictly on a concept known as Moore’s Law, which focused on physically shrinking transistors to squeeze more power onto a single piece of silicon. However, that traditional path is hitting severe physical roadblocks and becoming incredibly expensive. Because trade restrictions prevent the company from buying the most advanced chipmaking machines, Huawei is choosing a completely different engineering route.

The Tau Scaling Law proposes replacing geometric shrinking with time scaling. Instead of worrying about making components smaller, the company is focusing on reducing the exact amount of time it takes for electrical signals to move across circuits, chips, and entire computing systems. By compressing these internal transmission delays, the company can steadily improve overall chip performance without needing rare manufacturing equipment.

The roadmap to competitive hardware matching

The company revealed that this framework is not just a theoretical idea. Over the past six years, the chip division of the company has quietly designed and mass-produced 381 distinct chips utilizing this time-based method across consumer electronics and large-scale data networks. This foundational experience is giving the company high confidence in its future hardware delivery timeline.

According to official statements, the company expects its premium chips to achieve an operational transistor density equivalent to a highly advanced 1.4-nanometer process by the year 2031. This timeline puts the company on a highly competitive path to match major global foundries that are currently aiming to mass-produce their own 1.4-nanometer chips around late 2028.

Before that distant goal, the company will launch a new Kirin smartphone processor this upcoming autumn season that fully adopts a multilayer circuit design called LogicFolding. This immediate release will serve as the first mainstream consumer test for the new hardware philosophy, shaking up the smartphone processor market.