According to the latest information, Huawei intends to build a fab in Shenzhen with the power of SMIC, the largest foundry in China, and cut into wafer manufacturing through official funds, Huawei’s chip design capabilities, and SMIC.
At the recently opened SEMICON TAIWAN 2021 event, when major semiconductor equipment manufacturers showed off their own equipment, “Huawei wants to build a fab and get involved in wafer manufacturing” is a privately discussed topic in the industry.
According to industry estimates, Huawei’s initial investment in the construction of the factory is about tens of billions of dollars. Industry insiders believe that for Huawei, money is not a problem. The focus is on how to obtain abundant equipment and plant resources to quickly introduce mass production.
It is understood that Huawei has locked up relevant members of the “TSMC Alliance” this time, hoping to use the experience of past alliance members to assist TSMC’s fabs, shorten the learning curve of self-built fabs, and quickly enter mass production.
The TSMC major alliance includes major Taiwanese equipment consumables such as Jiadeng, Fanxuan, Hantang, and Zhongsha, but the members of the TSMC major alliance did not disclose information on the table.
The industry revealed that Huawei is looking for partners to promote its own fab plan, and will work with SMIC Southern. Due to the official funding support from the mainland, the investment amount of individual companies are still unclear, and how to bypass international patents and technologies is a problem. But it is still rumored that a factory will be built in Shenzhen to supply Huawei’s own needs.
It is worth noting that SMIC South was established with SMIC, SMIC Holdings, China National Fund, and Shanghai Integrated Circuit Fund. This time Huawei is preparing to build a fab, not only coercing Huawei itself.
According to the data, SMIC’s own shareholding ratio with official background exceeds 60%, indicating that it is not a single company’s strategy, but intends to use the official strategy for wafer manufacturing layout.